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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:53:02 04/26/2012 
-- Design Name: 
-- Module Name:    proyecto_aic - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.definitions.ALL;

entity proyecto_aic is
    Port (
			
            clk_i : in STD_LOGIC;
            clr_i : in STD_LOGIC;
            
            int_req : in STD_LOGIC;
            int_ack : out STD_LOGIC;
				data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
            data_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
end proyecto_aic;

architecture Behavioral of proyecto_aic is

    component Cyclone
        Port (
            clk_i : in STD_LOGIC;
            clr_i : in STD_LOGIC;
            instr_ack_i : in STD_LOGIC;
            instr_word_i : in STD_LOGIC_VECTOR (17 downto 0);
            data_ack_i : in STD_LOGIC;
            data_word_i : in STD_LOGIC_VECTOR (7 downto 0);
            port_ack_i : in STD_LOGIC;
            port_word_i : in STD_LOGIC_VECTOR (7 downto 0);
            int_req : in STD_LOGIC;
            int_ack : out STD_LOGIC;
            instr_cyc_o : out STD_LOGIC;
            instr_stb_o : out STD_LOGIC;
            instr_addr_o : out STD_LOGIC_VECTOR (9 downto 0);
            data_cyc_o : out  STD_LOGIC;
            data_stb_o : out  STD_LOGIC;
			   data_we_o : out STD_LOGIC; 
            data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
            data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
            port_cyc_o : out  STD_LOGIC;
            port_stb_o : out  STD_LOGIC;
            port_we_o : out  STD_LOGIC;
            port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
            port_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
    end component;

    component DataMemory
        Port ( 
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           data_addr_i : in  STD_LOGIC_VECTOR (7 downto 0);
           rw : in  STD_LOGIC;
           data_cyc_i : in  STD_LOGIC;
           data_stb_i : in  STD_LOGIC;
           data_ack_o : out  STD_LOGIC;
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
    end component;

    component InstructionMemory
        Port ( 
           instr_addr_i : in  STD_LOGIC_VECTOR (9 downto 0);
           instr_cyc_i : in  STD_LOGIC;
           instr_stb_i : in  STD_LOGIC; 		   clr : in STD_LOGIC;
           instr_word_o : out  STD_LOGIC_VECTOR (17 downto 0);
           instr_ack_o : out  STD_LOGIC);
    end component;

    signal instr_ack, data_ack, port_ack, instr_cyc, instr_stb, data_cyc,
            data_stb, data_we, port_cyc, port_stb, port_we: STD_LOGIC;
    signal instr_word: STD_LOGIC_VECTOR (17 downto 0);
    signal instr_addr: STD_LOGIC_VECTOR (9 downto 0);
    signal data_word_load, data_word_store, port_word_load, port_word_store,
            data_addr, port_addr: STD_LOGIC_VECTOR (7 downto 0);

begin
    cpu_cyclone: Cyclone Port map (
            clk_i, clr_i,
            instr_ack, instr_word, data_ack,
            data_word_load, port_ack, port_word_load,
            int_req, int_ack,
            instr_cyc, instr_stb, instr_addr,
            data_cyc, data_stb, data_we, data_addr, data_word_store,
            port_cyc, port_stb, port_we, port_addr, port_word_store
    );

    data_mem: DataMemory Port map (
            data_word_store, data_addr, data_we,
            data_cyc, data_stb, data_ack, data_word_load
    );

    port_mem: DataMemory Port map (
            port_word_store, port_addr, port_we,
            port_cyc, port_stb, port_ack, port_word_load
    );

    instr_mem: InstructionMemory Port map (
            instr_addr, instr_cyc, instr_stb,
            clr_i, instr_word, instr_ack
    );
	 
	 data_addr_o <= data_addr;
    data_word_o <= data_word_store;

end Behavioral;
